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Cases
Conferences General Home Page
Cases 2003 Conference Program:
2003 International Conference on
Compilers, Architectures
and Synthesis of Embedded Systems (CASES/03)
DoubleTree Hotel, San Jose, CA
Oct. 30 – Nov. 1, 2003
Final Program
Ppt links are currently not available, but will be made available in
the future.
DAY 1 – Thursday Oct. 30
8:00 –
8:30
Continental breakfast
8:30 –
8:45
Introduction
8:45 –
10:00
Keynote presentation, Josh Fisher, HP Labs,(pdf)
10:00 -
10:30
Coffee break
10:30 -
12:30
Session 1: Compilation (Chair: Jack Davidson)
Vectorizing for a SIMdD DSP Architecture(ppt)
Dorit Naishlos, Marina Biberstein, Shay Ben-David, Ayal Zaks, IBM Haifa
Labs, Haifa, Israel
Simple Offset Assignment in Presence
of Subword Data(ppt)Bengu Li, Rajiv Gupta, Department of Computer
Science, The University of Arizona, Tucson, USA
Efficient Spill Code for SDRAM (pdf)V
Krishna Nandivada, Jens Palsberg, Purdue University, USA
Cluster Assignment of Global Values for Clustered VLIW ProcessorsAndrei
Terechko, Erwan Le Thénaff, Philips Research, Eindhoven, The
Netherlands; Henk Corporaal, Technical University, Eindhoven, The
Netherlands
12:30 -
2:00
Lunch (provided)
2:00 -
4:00
Session2: Task Scheduling and Real-Time (Chair: Frank Mueller)
Extending STI for Demanding Hard-Real-Time Systems(pdf)
Benjamin Welch, Shobhit Kanaujia, Adarsh Seetharam,
Deepaksrivats Thirumalai, Alexander G. Dean, North Carolina State
University , Raleigh, USA
Clustered Calculation of Worst-Case
Execution Times
Andreas Ermedahl, Mälardalen Real-Time Research Center,
Västerås, Sweden; Friedhelm Stappert, C-LAB, Paderbon,
Germany; Jakob Engblom, Virtutech, Stockholm, Sweden
Task-level Timing Models for
Guaranteed Performance in Multiprocessor Networks-on-Chip (ppt)
P. Poplavko, T. Basten, Department of Electrical Engineering, Eindhoven
University of Technology; M. Bekooij, Philips Research Laboratories,
Eindhoven; J. van Meerbergen, B. Mesman, Department of Electrical
Engineering, Eindhoven University of Technology, Eindhoven, The
Netherlands
System-Level Power-Performance
Trade-Offs in Task Scheduling for Dynamically Reconfigurable
Architectures (pdf)
Juanjo Noguera, Hewlett-Packard InkJet Commercial Division, Barcelona,
Spain;
Rosa M. Badia, Computer Architecture Department, Technical University
of Catalonia (UPC), Barcelona, Spain
4:00 -
4:30
Coffee break
4:30 –
6:00
Session 3: Code Compression (Chair: Wei Zhao)
Reducing Code Size With Echo Instructions
Jeremy Lau, Stefan Schoenmackers, Department of Computer Science and
Engineering, University of California San Diego; Timothy Sherwood,
Department of Computer Science, University of California Santa Barbara;
Brad Calder, Department of Computer Science and Engineering, University
of California San Diego, USA
Compiler Optimization and Ordering
Effects on VLIW Code Compression
Montserrat Ros, Peter Sutton, School of Information Technology and
Electrical Engineering, The University of Queensland, Brisbane,
Australia
Reducing Code Size for
Heterogeneous-Connectivity-Based VLIW DSPs through Synthesis of
Instruction Set Extensions (ppt) Partha Biswas, Nikil Dutt,
Center for Embedded Computer Systems, University of California, Irvine,
USA
6:00 –
7:00
Invited speaker, Prof. Krishna PalemGeorgia Institute of Technology,
Atlanta, USA
”Energy Aware Algorithm Design via Probabilistic Computing: From
Algorithms and Models to Moore’s Law and Novel (Semiconductor)
Devices”
7:00 –
8:00
Reception (sponsored by Fujitsu)
DAY 2 – Friday Oct. 31
8:00 –
8:30
Continental breakfast
8:30 -
10:30
Session 4: Microprocessor Architecture (Chair: Walid Najjar)
Frequent Loop Detection Using Efficient Non-Intrusive On-Chip Hardware
(ppt)
Ann Gordon-Ross and Frank Vahid, Department of Computer Science and
Engineering, University of California Riverside, USA
Increasing the Number of Effective
Registers in a LowPower Processor Using a Windowed Register File(ppt)
Rajiv Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika,
Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown, Department
of Electrical Engineering and Computer Science, University of
Michigan Ann Arbor, USA
Automatic Generation of Application
Specific Processors(pdf)
David Goodwin, Darin Petkov, Tensilica, USA
A Scalable Wide-Issue Clustered VLIW
with a Reconfigurable Interconnect (pdf)
Osvaldo Colavin, Davide Rizzo, STMicroelectronics, Inc., San Diego, USA
10:30 –
11:00
Coffee break
11:-00 –
12:30
Session 5: Emerging Areas (Chair: Boon Ang)
A New Look at Exploiting Data Parallelism in Embedded Systems (ppt)
Hillery Hunter, Department of Electrical and Computer Engineering,
University of Illinois, Urbana-Champaign;
J.H. Moreno, IBM Thomas J. Watson Research Center, Yorktown Heights, USA
Fault Tolerant Platforms for
Automotive Safety Critical Applications
Massimo Baleani, A. Ferrari, L. Mangeruca, A. Sangiovanni-Vincentelli,
PARADES EEIG, Rome, Italy; Maurizio Peri, Saverio Pezzini, ST
Microelectronics, Agrate Brianza, Italy
Programming Challenges in Network Processor Deployment,(pdf)
Chidamber Kulkarni, Matthias Gries, Christian Sauer, Kurt Keutzer,
Electronics Research Laboratory, University of California, Berkeley, USA
12:30 –
2:00
Lunch (provided)
2:00 –
4:00
Session 6: Embedded Applications (Chair: Kees Vissers)
Encryption Overhead in Embedded Systems and Sensor Network Nodes:
Modeling and Analysis (ppt)
R. Venugopalan, P. Ganesan, P. Peddabachagari, A. Dean, F. Mueller, M.
Sichitiu, Center for Embedded Systems Research, North Carolina State
University, Raleigh, USA
AES and The Cryptonite Crypto
Processor
Dino Oliva, Rainer Buchty, Nevin Heintze, Agere Systems, Holmdel, USA
A Low Power Accelerator for the SPHINX 3 Speech Recognition Systema(ppt)
Binu Mathew, Al Davis, Zhen Fang, School of Computing, University of
Utah, Salt Lake City, USA
Architectural Optimizations for
Low-Power, Real-Time Speech Recognition
Rajeev Krishna, Scott Mahlke, and Todd Austin, Advanced Computer
Architecture Lab, University of Michigan, Ann Arbor, USA
4:00 –
4:30
Coffee break
4:30 -
6:30
Session 7: Power and Energy (Chair: Trevor Mudge)
Graphical User Interface Energy Characterization for Handheld
Computers(ppt)
Lin Zhong, Niraj K. Jha, Department of Electrical Engineering,
Princeton University, Princeton, USA
A Hierarchical Approach for Energy
Efficient Application Design Using Heterogeneous Embedded Systems
Sumit Mohanty, Viktor K. Prasanna, University of Southern California,
Los Angeles, USA
A Control-Theoretic Approach to
Dynamic Voltage Scheduling
Ankush Varma, Brinda Ganesh, Mainak Sen, Suchismita Roy Choudhury,
Lakshmi Srinivasan, and Bruce Jacob, Department of Electrical and
Computer Engineering, University of Maryland, College Park, USA
Power Efficient Encoding Techniques
for Off-chip Data BusesDinesh C Suresh, Banit Agrawal, Jun Yang, Walid
Najjar, Laxmi Bhuyan, Computer Science and Engineering,
University of California, Riverside, USA
DAY 3 – Saturday Nov. 1
8:00 –
8:30
Continental breakfast
8:30 -
11:00
Session 8: Memory Hierarchy (Chair: Scott Mahlke)
Compiler Decided Dynamic Memory Allocation for Scratch-Pad Based
Embedded Systems(ppt)
Sumesh Udayakumaran, Rajeev Barua, Department of Electrical and
Computer Engineering, University of Maryland, College Park, USA
Exploiting Bank Locality in
Multi-Bank Memories
U. Sezer, Department of Electrical and Computer Engineering, University
of Wisconsin, Madison, USA; G. Chen, M. Kandemir, H. Saputra, M.
J. Irwin, Department of ComputerScience and Engineering, The
Pennsylvania State University, USA
Lattice-Based Memory Allocation(ppt)
Alain Darte, CNRS LIP ENS-Lyon, Lyon, France; Rob Schreiber, Hewlett
Packard Laboratories, Palo Alto, USA; Gilles Villard, CNRS LIP
ENS-Lyon, Lyon, France
Performance, Energy, and Reliability Tradeoffs in Replicating Hot Cache
Lines
W. Zhang, M. Kandemir, A. Sivasubramanian, M.J. Irwin, Department of
Computer Science and Engineering, The Pennsylvania State University,
University Park, USA
Polynomial Time Algorithm for On-Chip Scratchpad Memory
Partitioning(ppt)
Federico Angiolini, Luca Benini, Alberto Caprara, University of
Bologna, DEIS, Bologna, Italy
11:00 -
11:30
Coffee break
11:30 -
12:00
Wrap-up / business meeting
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