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2004 Conference Program:
2004 International Conference on
Compilers, Architectures
and Synthesis of Embedded Systems
(CASES/04)
The Latham Hotel, Washington D.C., USA
Sept. 22 – Sept. 25, 2004
Final
Program
Main Conference Program
Thursday, Sept. 23
08:00 -
08:30
Continental breakfast
08:15 -
08:30
Welcome
1. General Co-Chairs – Mary Jane Irwin and Wei Zhao
2. Program Co-Chairs – Luciano Lavagno and Scott
Mahlke
08:30
-
09:30
Keynote Presentation I
1. Programming Models and Architectures for FPGA Platforms [abstract]
Kees Vissers – Xilinx Research, San Jose, USA
09:30 -
10:00
Coffee break
10:00
-
12:00
Session 1: Memory Systems (Session Chair: Trevor Mudge, University of
Michigan)
1. Safely Exploiting Multithreaded Processors to Tolerate Memory
Latency in
Real-Time Systems
Ali
El-Haj-Mahmoud and Eric Rotenberg – North Carolina State
University,
Raleigh, USA
2. Dynamic On-Chip Memory Management for Chip Multiprocessors
Mahmut Kandemir
and Ozcan Ozturk – Pennsylvania State University, University
Park, USA
3. Cluster Miss Prediction with Prefetch on Miss for Embedded CPU
Instruction
Caches
Ken
Batcher and Robert Walker – Kent State University, Kent, USA
4. Reducing Energy Consumption of Queries in Memory-Resident Database
Systems
Jayaprakash
Pisharath and Alok Choudhary – Northwestern University,
Evanston, USA; Mahmut Kandemir - Pennsylvania State
University, University
Park, USA
12:00 -
13:30
Lunch (provided)
13:30
-
15:30
Session 2: Application Specific Processors (Session Chair: Krisztian
Flautner, Arm Ltd)
1. A Low Power Architecture for Embedded Perception
Binu
Mathew, Al Davis, and Mike Parker – University of Utah, Salt Lake
City, USA
2. Balancing Design Options with Sherpa
Timothy
Sherwood – University of California Santa Barbara, Santa Barbara,
USA; Mark Oskin – University of Washington, Seattle, USA;
Brad Calder –
University of California San Diego, San Diego, USA
3. Scalable Custom Instructions Identification for Instruction-Set
Extensible Processors
Pan
Yu and Tulika Mitra – National University of Singapore, Singapore
4. LNS Architectures for Embedded Model Predictive Control Processors
Jesus Garcia and Mark Arnold – Lehigh University,
Bethlehem, USA
15:30 -
16:00
Coffee break
16:00
-
18:00
Session 3: Low Power SOCs and NOCs (Session Chair: Alex Dean, North
Carolina State University)
1. Plug-in of Power Models in the StepNP Exploration Platform: Analysis
of
Power/Performance Trade-offs
Giovanni
Beltrame, Gianluca Palermo, Donatella Sciuto, and Cristina Silvano
–
Politecnico di Milano, Milano, Italy
2. Disk Drive Energy Optimization for Audio-Video Applications
Ravishankar
Rao and Sarma Vrudhula – University of Arizona, Tucson, USA;
Musaravakkam Krishnan – Portal Player, Santa Clara,
USA
3. Power Analysis of On-Chip Networks
Noel
Eisley and Li-Shiuan Peh – Princeton University, Princeton, USA
4. Energy-Efficient Dual-Voltage Soft Real-Time System with (m,k)-Firm
Deadline
Guarantee
Shaoxiong
Hua and Gang Qu – University of Maryland, College Park, USA
18:00 -
19:30
Reception and Panel Session
Friday, Sept. 24
08:00 -
08:30
Continental breakfast
08:30
-
10:30
Session 4: Low Power Processors (Session Chair: Hsien-Hsin Lee, Georgia
Institute of Technology)
1. Static Next Sub-bank Prediction for Drowsy Instruction Cache
Wei Zhang
and Bramha Allu – Southern Illinois University, Carbondale, USA
2. A Hamming Distance Based VLIW/EPIC Code Compression Technique
Montserrat
Ros and Peter Sutton – University of Queensland, Queensland,
Australia
3. Reducing Both Dynamic and Leakage Energy Consumption for Hard
Real-Time Systems
Linwei
Niu and Gang Quan – University of South Carolina, Columbia, USA
4. Loop-based Leakage Control for Branch Predictors
Wei Zhang
and Bramha Allu – Southern Illinois University, Carbondale, USA
10:30 -
11:00
Coffee break
11:00
-
12:00
Keynote Presentation II
2. Balanced Energy Optimization [abstract]
John Cornish – ARM Limited, Cambridge,
England
12:00 -
13:30
Lunch (provided)
13:30
-
15:30
Session 5: Compiler Analysis and Optimization (Session Chair: Jack
Davidson, University of Virginia)
1. Static Program Analysis of Embedded Executable Assembly Code
Ramakrishnan
Venkitaraman and Gopal Gupta – University of Texas at Dallas,
Dallas, USA
2. Providing Time- and Space- Efficient Procedure Calls for
Asynchronous
Software Thread Integration
Vasanth
Asokan and Alex Dean – North Carolina State University, Raleigh,
USA
3. Causality Analysis of Synchronous Programs with Delayed Actions
Klaus
Schneider, Jens Brandt, and Tobias Schuele – University of
Kaiserslautern, Kaiserslautern, Germany
4. General Loop Fusion Technique for Nested Loops Considering Timing
and Code Size
Meilin Liu,
Qingfeng Zhuge, Zili Shao, and Edwin H.-M. Sha – University of
Texas
at Dallas, Dallas, USA
15:30 -
16:00
Coffee break
16:00
-
18:00
Session 6: Co-Design and Synthesis (Session Chair: Bart Kienhuis,
Leiden University)
1. Modular Design Through Component Abstraction
David
Berner and Jean-Pierre Talpin – INRIA-IRISA, Rennes, France;
Sandeep
Shukla – Virginia Tech University, Blacksburg, USA;
Paul Le Guernic –
INRIA-IRISA, Rennes, France
2. An Efficient System-on-a-Chip Design Methodology for Networking
Applications
Valentina
Salapura, Christos J. Georgiou, Indira Nair – IBM T.J. Watson
Research Center, Yorktown, USA
3. Translating Affine Nested-Loop Programs to Process Networks
Alexandru
Turjan, Bart Kienhuis, Ed Deprettere –Leiden University, Leiden,
The
Netherlands
4. Memory and Architecture Exploration with Thread Shifting for
Multithreaded
Processors in Embedded Systems
Mary
Kiemb and Kiyoung Choi –Seoul National University, Seoul, South
Korea
18:00 -
19:30
CASES business meeting
Saturday, Sept. 25
08:00 -
08:30
Continental breakfast
08:30
-
10:30
Session 7: Memory Optimization (Session Chair: Alain Darte, Ecole
Normale Superireure de Lyon)
1. Automatic Data Partitioning for the Agere Payload Plus Network
Processor
Steve Carr
– Michigan Technological University, Houghton, USA; Philip Sweany
– University of North Texas, Denton, USA
2. Analytical Computation of Ehrhart Polynomials: Enabling more
Compiler
Analyses and Optimizations
Sven
Verdoolaege –K. U. Leuven, Belgium; Rachid Seghir – ICPS,
Strasbourg,
France; Kristof Beyls – Ghent University, Belgium; Vincent
Loechner – ICPS,
Strasbourg, France; Maurice Bruynooghe – K. U. Leuven,
Belgium
3. A Post-Compiler Approach to Scratchpad Mapping of Code
Federico
Angiolini –Universita' di Bologna, Bologna, Italy; Francesco
Menichelli
– Universita' di Roma, Roma, Italy; Luca Benini
–Universita' di Bologna,
Bologna, Italy
4. Procedure Placement Using Temporal Ordering Information: Dealing
with Code
Size Expansion
Thierry
Bidault and Christophe Guillon – ST Microelectronics, France;
Florent
Bouchez and Fabrice Rastello – Ecole Normale Superireure
de Lyon, Lyon,
France
10:30 -
11:00
Coffee break
11:00
-
12:30
Session 8: Reliability and Security (Session Chair: Timothy Sherwood,
University of California Santa Barbara)
1. Memory Overflow Protection in Embedded Systems using Run-time
Checks,
Reuse and Compression
Surupa
Biswas – University of Maryland, College Park, USA; Matthew
Simpson –
Clemson University, Clemson, USA; Rajeev Barua –
University of Maryland,
College Park, USA
2. Hardware Assisted Control Flow Obfuscation for Embedded Processors
[Best
Paper Awarded]
Xiaotong
Zhuang, Tao Zhang, Hsien-Hsin Lee, and Santosh Pande – Georgia
Institute of Technology, Atlanta, USA
3. Java Cryptography on KVM and its Performance and Security
Optimization using
HW/SW Co-design Techniques
Yusuke
Matsuoka, Patrick Schaumont, Kris Tiri, and Ingrid Verbauwhede –
UCLA, Los Angeles, USA
12:30 -
13:00
Closing, Best paper award
