Speaker: Kees Vissers
Affiliation: Xilinx Research
2100 Logic Drive
San Jose, CA 95124
Title: Programming models and architectures for FPGA platforms.
Modern Platform FPGAs contain a combination of processors, embedded memory, programmable interconnect, dedicated DSP elements, and conventional lookup tables. On top of that they have multiple clock domains, very high speed Serial I/Os and a large number of pins.
This talk will focus on the programming of these systems. Conventional general purpose processors have been successfully programmed with sequential, control dominated programming languages like C and C++. This programming style has been succesfull for high-end DSPs, only after the architecture of the DSPs were tuned. This tuning required the interaction between compiler writers and processor architects.
Todays conventional FPGAs are programmed with VHDL or Verilog. The semantics of these languages enable significant current systems at the expense of relatively low-level, explicit timing oriented programming.
The existing notion of Dataflow models should be very good for expressing concurrency in high-end DSP systems. One of the first programming environments for FPGAs that exploit this is the Matlab/Simulink environment.
This talk will show how the various dataflow models can be exploited to build more powerfull programming environments for todays FPGAs. In particular the combination of programming models and the systematic design of architecture elements is extremely powerfull. The talk will finish by showing the interesting research directions that can have a significant impact on the design of future FPGA platforms. The various approaches will be illustrated with facts and figures from actual designs, including JPEG2000 and MPEG4 encoders and decoders.