Sep 22, 2004

Washington D.C

Final Program


Workshop on Media and Signal Processors for Embedded Systems and SoCs

Held in conjunction with the 2004 International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES 2004).

Embedded media, communications, and signal processing continues to become an increasingly ubiquitous part of everyday life. However, the design of such systems is often characterized by low cost, high computational complexity and power efficiency requirements, as well as the growing demand for greater functionality and application flexibility, and simpler integration with other embedded systems. These complex and often conflicting design goals require significant advances in architectures, compilers, and design tools for these systems. The Workshop on Media and Signal Processors for Embedded Systems and SoCs (MASES), held in conjunction with CASES 2004 in Washington D.C., provides a forum for investigating media algorithms and applications, processor and system architectures, as well as design methodology and tools for future media, communications, and signal processing systems.

Technical Program Co-Chairs
Eric Debes

Sethuraman Panchanathan
   Arizona State University

Technical Program Commitee
Shuvra S. Bhattacharyya
   University of Maryland

V. Michael Bove, Jr.

Wayne Burleson
   University of Massachusetts, Amherst

Liang-Gee Chen
   National Taiwan University

Jose Fridman
   Analog Devices

Jason Fritts
    Washington University in St Louis

Rajesh Gupta
   University of California, San Diego

Paolo Ienne
   Swiss Federal Institute of Technology (EPFL)

Peter Pirsch
   University of Hannover

Sudha Sudharsanan
    Queens University

Wayne Wolf


Prospective authors are invited to submit manuscripts on topics including but not limited to:

  • Image, video and multimedia Processors
  • DSP architectures
  • SoC architectures for media and communication applications
  • SoC design tools
  • Hardware/Software Codesign
  • Platform-based design methodology
  • SoC Interconnects, network-on-chip
  • Low-power media processors and SoC architectures
  • Intelligent memory architectures for media applications
  • Simulations of media and communication architectures
  • Static and dynamic reconfigurability in media architectures
  • Workload Characterization of media and communication applications
  • Optimization and performance analysis of media processor architectures

Submission of Papers
Paper will be accepted on the basis of an extended abstract of 6 pages that describes the work, its significance and the current status of the research. Paper should represent original work not published or submitted for publication in other forums. Please visit the Submissions page for submission instructions." The final paper should not be longer than 10 pages (including figures, references and appendices) in 12pt font. All accepted papers will be presented at the workshop and included in informal proceedings that will be distributed at the workshop. In addition, accepted papers will be made available on the workshop homepage. A PDF version of the Call for paper is available here.



June 1, 2004

Author Notif.

July 15, 2004

Camera Ready

Aug 15, 2004

Advanced Registration Deadline

Aug 15, 2004